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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9747979 B1

PDFFull Text
Date of Patent:
Aug. 29, 2017

Filed:

Aug. 13, 2015

Nonvolatile semiconductor storage device including cell transistor performance measuring cells

Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Masayoshi Nakayama, Kyoto, JP;

Kazuyuki Kouno, Osaka, JP;

Reiji Mochida, Osaka, JP;

Keita Takahashi, Nara, JP;

Assignee:

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD., Osaka, JP;

Attorney:

McDermott Will & Emery LLP

Primary Examiner:

Amir Zarabian

Assistant Examiner:

Roberto Mancera, Jr

Int. Cl.
CPC ...
G11C 11/16 (2006.01); G11C 7/14 (2006.01); G11C 8/08 (2006.01); G11C 29/24 (2006.01); G11C 13/00 (2006.01); H01L 27/10 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 7/14 (2013.01); G11C 8/08 (2013.01); G11C 11/16 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 13/0002 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0038 (2013.01); G11C 13/0069 (2013.01); G11C 29/24 (2013.01); H01L 27/101 (2013.01); H01L 27/2436 (2013.01); H01L 45/04 (2013.01); H01L 45/1233 (2013.01); G11C 2013/0054 (2013.01); G11C 2013/0071 (2013.01); G11C 2013/0073 (2013.01); G11C 2029/1202 (2013.01); G11C 2213/79 (2013.01); G11C 2213/82 (2013.01);
Abstract

A memory array includes a plurality of memory cells arranged in a matrix, each memory cell including a cell transistor and a variable resistance element connected to an end of the cell transistor, and a cell transistor performance measuring cell including a MOS transistor. The cell transistor performance measuring cell is used to stabilize resistance values in a low resistance state and a high resistance state of the variable resistance element irrespective of variations in the cell transistor and thereby improve read characteristics and reliability characteristics of a nonvolatile semiconductor storage device.

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