The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

Jul. 03, 2014
Applicant:

Avago Technologies General Ip (Singapore) Pte. Ltd, Singapore, SG;

Inventors:

Saugata Das Purkayastha, Bangalore, IN;

Kishore Kaniyar Sampathkumar, Bangalore, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 13/28 (2006.01); G06F 13/42 (2006.01); G06F 12/02 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 12/0238 (2013.01); G06F 13/1694 (2013.01); G06F 13/4221 (2013.01); G06F 2212/202 (2013.01);
Abstract

Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD for cache operations. The DRAM and the SSD are sectioned into pages and mapped to pages of the host memory. The SSD is further sectioned into regions comprising one or more pages of the SSD. AnHBA driver is operable to load a page of data from the SSD into a page of the DRAM when directed by a host processor, to determine that the page of the DRAM is occupied with other data, to determine a priority of the region of the page of other data occupying the page of the DRAM, and to flush the other data from the DRAM to the SSD based on the determined priority.


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