Amorphous silicon semiconductor tft backboard structure

Abstract

The present invention provides an amorphous silicon semiconductor TFT backboard structure, which includes a semiconductor layer () that has a multi-layer structure including a bottom amorphous silicon layer () in contact with a gate insulation layer (), an N-type heavily-doped amorphous silicon layer () in contact with a source electrode () and a drain electrode (), at least two N-type lightly-doped amorphous silicon layers () sandwiched between the bottom amorphous silicon layer () and the N-type heavily-doped amorphous silicon layer (), a first intermediate amorphous silicon layer () separating every two adjacent ones of the lightly-doped amorphous silicon layers (), and a second intermediate amorphous silicon layer () separating the N-type heavily-doped amorphous silicon layer () from the one of the lightly-doped amorphous silicon layers () that is closest to the N-type heavily-doped amorphous silicon layer (). Such a structure further reduces the energy barrier between the drain electrode and the semiconductor layer, making injection of electron easier and ensuring the ON-state current is not lowered down and also helping increase the barrier for transmission of holes, lowering down the leakage current and improving reliability and electrical stability of the TFT.