Approach for an area-efficient and scalable cmos performance based on advanced silicon-on-insulator (soi), silicon-on-sapphire (sos) and silicon-on-nothing (son) technologies

Abstract

New, distinct, and useful architectures for single-legged SOI-MOS were established and fabricated for the very first time. They incorporated into their architectures an innovative new configuration to wire the device Body to the Body-Tied-Source. This new configuration drastically increased the conductance between the Body and the Body-Tied-Source. This consequently allowed these devices to effectively support much higher operating biases. Same configuration also functioned on structures with very large peripheries. These gave proportional increase in this same conductivity, and for same area-efficiency, with the increase of their peripheries to accommodate higher currents. The functional model that governs this proportional scaling in these new architectures for single-legged SOI-MOS devices was established and is being claimed through this patent for the very first time. Through it, single-legged SOI-MOS devices will efficiently scale to area-efficient ultra large peripheries with minimal hits to their bandwidth.