The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

Apr. 19, 2016
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Luiz M. Franca-Neto, Sunnyvale, CA (US);

Jeffrey Lille, Sunnyvale, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); G11C 13/00 (2006.01); H01L 27/06 (2006.01); H01L 27/11551 (2017.01); H01L 27/11578 (2017.01);
U.S. Cl.
CPC ...
H01L 27/249 (2013.01); G11C 13/004 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01); H01L 27/0688 (2013.01); H01L 27/11551 (2013.01); H01L 27/11578 (2013.01); H01L 27/2427 (2013.01); H01L 27/2481 (2013.01); H01L 45/065 (2013.01); H01L 45/085 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/141 (2013.01); H01L 45/146 (2013.01); H01L 45/1616 (2013.01);
Abstract

Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.


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