The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

May. 11, 2016
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventor:

Kenichi Murooka, San Jose, CA (US);

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); G11C 5/06 (2006.01); G11C 5/02 (2006.01); G11C 13/00 (2006.01); G11C 7/10 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2481 (2013.01); G11C 5/02 (2013.01); G11C 5/06 (2013.01); G11C 5/063 (2013.01); G11C 7/1006 (2013.01); G11C 13/0002 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0023 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); H01L 21/768 (2013.01); H01L 27/2454 (2013.01); H01L 29/66666 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); H01L 45/149 (2013.01); H01L 45/1608 (2013.01); G11C 2213/31 (2013.01); G11C 2213/32 (2013.01); G11C 2213/35 (2013.01); G11C 2213/71 (2013.01); G11C 2213/78 (2013.01);
Abstract

According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.


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