logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9741628 B1

PDFFull Text
Date of Patent:
Aug. 22, 2017

Filed:

Oct. 07, 2015

Method for manufacturing semiconductor module and intermediate assembly unit of the same

Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, Kanagawa, JP;

Inventor:

Kenichiro Sato, Shiojiri, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-shi, JP;

Attorney:

Manabu Kanesaka

Primary Examiner:

Jose R Diaz

Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 21/66 (2006.01); H01L 21/48 (2006.01); H01L 29/16 (2006.01); H01L 29/872 (2006.01); H01L 29/739 (2006.01); H01L 25/11 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01); H01L 23/498 (2006.01); H01L 23/057 (2006.01); H01L 23/373 (2006.01);
U.S. Cl.
CPC ...
H01L 22/14 (2013.01); H01L 21/4889 (2013.01); H01L 23/49811 (2013.01); H01L 23/49844 (2013.01); H01L 24/40 (2013.01); H01L 25/072 (2013.01); H01L 25/115 (2013.01); H01L 29/1608 (2013.01); H01L 29/7393 (2013.01); H01L 29/872 (2013.01); H01L 23/057 (2013.01); H01L 23/3735 (2013.01); H01L 23/49866 (2013.01); H01L 25/18 (2013.01); H01L 2224/40095 (2013.01); H01L 2224/40137 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/13055 (2013.01);
Abstract

A method for manufacturing a semiconductor module includes the step of soldering two or more semiconductor elements having substrate materials and heights different from each other to a metal foil disposed at one side of an insulating substrate; connecting a plurality of wiring members, not interconnecting the semiconductor elements, to front face electrodes of the semiconductor elements through solder so that heights from a surface of the insulating substrate to top faces of the wiring members become same level with each other; inspecting a leakage current while applying electricity on each one of semiconductor elements individually through the wiring members; and connecting the top faces of the wiring members with a bus bar.

Find Patent Forward Citations

Loading…