The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

Jul. 08, 2016
Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, JP;

Inventors:

Tsunehiro Nakajima, Matsumoto, JP;

Yoshikazu Takahashi, Matsumoto, JP;

Norihiro Nashida, Nagano, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-Shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 25/00 (2006.01); H01L 21/321 (2006.01); H01L 23/492 (2006.01); H01L 25/065 (2006.01); H01L 21/283 (2006.01); H01L 23/00 (2006.01); H01L 23/373 (2006.01); H01L 23/482 (2006.01); H01L 21/683 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 21/32115 (2013.01); H01L 21/283 (2013.01); H01L 21/6835 (2013.01); H01L 21/6836 (2013.01); H01L 23/3735 (2013.01); H01L 23/482 (2013.01); H01L 23/492 (2013.01); H01L 24/24 (2013.01); H01L 24/34 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 23/49811 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01); H01L 2224/24137 (2013.01);
Abstract

Provided are a semiconductor device manufacturing method and semiconductor device such that manufacturing can be simplified and the thickness of the semiconductor device can be reduced. The semiconductor device includes an insulated circuit substrate having on one main surface thereof a first metal layer and a second metal layer, a metal plate conductively connected to the first metal layer, a first semiconductor element including on front and rear surfaces thereof a plurality of metal electrodes, a first insulating member disposed on a side surface of the first semiconductor element, a second insulating member disposed on the first insulating member and on the first semiconductor element, and a third metal layer, in which at least one portion thereof is disposed on the second insulating member and which conductively connects the metal electrode of the first semiconductor element and the second metal layer on the insulated circuit substrate.


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