Semiconductor memory device having dummy word lines and operating method thereof

Abstract

A semiconductor memory device includes a memory cell array, and a voltage generator suitable for generating voltages supplied to the memory cell array. The memory cell array includes cell strings each including memory cells extending in a first direction and arranged in a second direction and a third direction; bit lines extending in the second direction and electrically coupled to the cell strings; and word lines extending in the third direction and electrically coupled to corresponding memory cells, wherein the word lines includes dummy word lines. A program voltage is supplied to a program word line that is electrically coupled to a memory cell to be programmed, and a level of a first dummy word line voltage supplied to a parallel dummy word line, which is disposed parallel to the program word line in the first direction is different from a level of a second dummy voltage supplied to a nonparallel dummy word line other than the parallel dummy word line.