The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

Nov. 02, 2016
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Shuhei Nagatsuka, Kanagawa, JP;

Tomokazu Yokoi, Kanagawa, JP;

Naoaki Tsutsui, Kanagawa, JP;

Kazuaki Ohshima, Kanagawa, JP;

Tatsuya Onuki, Kanagawa, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/06 (2006.01); H01L 27/11582 (2017.01); H01L 27/11568 (2017.01); G11C 5/06 (2006.01); G11C 8/10 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G11C 7/065 (2013.01); G11C 5/063 (2013.01); G11C 7/10 (2013.01); G11C 7/12 (2013.01); G11C 8/10 (2013.01); H01L 27/11568 (2013.01); H01L 27/11582 (2013.01);
Abstract

A semiconductor device or a memory device with a reduced area, a large storage capacity, a high-speed operation, or low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, a first wiring, a second wiring, a sense amplifier circuit, a decoder, a step-up circuit, a level shifter, and a buffer circuit. The first wiring is electrically connected to the buffer circuit and a second gate electrode of the first transistor. The second wiring is electrically connected to the sense amplifier circuit and the drain electrode of the second transistor. The capacitor is electrically connected to the drain electrode of the first transistor and the source electrode of the second transistor.


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