The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

Jul. 17, 2016
Applicant:

Everspin Technologies, Inc., Chandler, AZ (US);

Inventors:

Syed M. Alam, Austin, TX (US);

Thomas Andre, Austin, TX (US);

Dietmar Gogl, Austin, TX (US);

Assignee:

EVERSPIN TECHNOLOGIES, INC., Chandler, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 11/4076 (2006.01); G11C 8/04 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G11C 11/16 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 14/00 (2006.01); G06F 13/16 (2006.01); G11C 11/4091 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0611 (2013.01); G06F 3/0685 (2013.01); G06F 12/0246 (2013.01); G06F 12/0638 (2013.01); G06F 13/1694 (2013.01); G11C 7/1042 (2013.01); G11C 7/1072 (2013.01); G11C 8/04 (2013.01); G11C 11/005 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/4076 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 14/0036 (2013.01); G06F 2212/205 (2013.01); G06F 2212/7201 (2013.01); G11C 11/16 (2013.01);
Abstract

A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.


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