The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

Oct. 24, 2014
Applicant:

National Instruments Corporation, Austin, TX (US);

Inventors:

Tai A. Ly, Austin, TX (US);

Swapnil D. Mhaske, Highland Park, NJ (US);

Hojin Kee, Austin, TX (US);

Adam T. Arnesen, Pflugerville, TX (US);

David C. Uliana, Austin, TX (US);

Newton G. Petersen, Emporia, KS (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); H03M 13/11 (2006.01); G06F 11/10 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01); H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0616 (2013.01); G06F 3/064 (2013.01); G06F 3/0622 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 11/1076 (2013.01); G06F 13/1615 (2013.01); G06F 13/1626 (2013.01); G11C 7/1039 (2013.01); H03M 13/1102 (2013.01); H03M 13/114 (2013.01); H03M 13/6563 (2013.01); H03M 13/6566 (2013.01); H03M 13/6569 (2013.01); Y02B 60/1228 (2013.01);
Abstract

Techniques are disclosed relating to configuring an interlock memory system. In one embodiment, a method includes determining a sequence of memory access requests for a program and generating information specifying memory access constraints based on the sequence of memory accesses, where the information is usable to avoid memory access hazards for the sequence of memory accesses. In this embodiment, the method further includes configuring first circuitry using the information, where the first circuitry is included in or coupled to a memory. In this embodiment, after the configuring, the first circuitry is operable to perform memory access requests to the memory corresponding to the sequence of memory accesses while avoiding the memory access hazards, without receiving other information indicating the memory access hazards.


Find Patent Forward Citations

Loading…