The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

Dec. 06, 2016
Applicant:

Marvell World Trade Ltd., St. Michael, BB;

Inventors:

Olivier Burg, Lausanne, CH;

Haisong Wang, Crissier, CH;

Xiang Gao, Fremont, CA (US);

Assignee:

Marvell World Trade Ltd., St. Michael, BB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/50 (2006.01); G04F 10/00 (2006.01); H03M 1/00 (2006.01); H04M 1/50 (2006.01); H03M 1/12 (2006.01); H03B 21/02 (2006.01); H03L 7/089 (2006.01);
U.S. Cl.
CPC ...
G04F 10/005 (2013.01); H03B 21/02 (2013.01); H03L 7/0891 (2013.01); H03M 1/00 (2013.01); H03M 1/12 (2013.01); H03M 2201/4233 (2013.01); H04M 1/505 (2013.01);
Abstract

A digital phase locked loop (DPLL) circuit includes a digital-to-time converter (DTC) configured to generate a delayed reference clock signal by delaying a reference clock signal according to a delay control signal and a time-to-digital converter (TDC) coupled to an output of the DTC. The TDC is configured to sample a value of a transition signal according to the delayed reference clock signal and to generate an output signal indicating a phase difference between the delayed clock signal and an input clock signal. A method of controlling a DPLL includes delaying a reference clock signal according to a delay control signal, sampling a value of a transition signal according to the delayed reference clock signal, generating an output signal indicating a phase difference between the delayed clock signal and an input clock signal, and generating a digitally controlled oscillator (DCO) clock signal according to the output signal.


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