The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2017
Filed:
Jun. 17, 2016
Electronics and Telecommunications Research Institute, Daejeon, KR;
Ja Yol Lee, Nonsan-si, KR;
Minjae Lee, Gwangju, KR;
Cheon Soo Kim, Daejeon, KR;
Jaehyun Kang, Cheongju-si, KR;
Junsoo Ko, Namyangju-si, KR;
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, Daejeon, KR;
Abstract
Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.