The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2017
Filed:
Sep. 30, 2013
Applicant:
Hitachi, Ltd., Chiyoda-ku, Tokyo, JP;
Inventors:
Yusuke Kanno, Tokyo, JP;
Nobuyasu Kanekawa, Tokyo, JP;
Kotaro Shimamura, Tokyo, JP;
Tadanobu Toba, Tokyo, JP;
Teppei Hirotsu, Tokyo, JP;
Tsutomu Yamada, Tokyo, JP;
Assignee:
Hitachi, Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); H03K 19/21 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17764 (2013.01); H03K 19/1776 (2013.01); H03K 19/17728 (2013.01); H03K 19/21 (2013.01);
Abstract
An object of the present invention is to provide a high reliable/high safe programmable logic device with high error resistance. The present invention provides a programmable logic device that has a plurality of configuration memories. The configuration memories are divided into a plurality of areas and are arranged and a part of the plurality of areas is set to a high reliable area where reliability of the configuration memory is higher than in the other area.