The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

Aug. 20, 2014
Applicant:

Altera Corporation, San Jose, CA (US);

Inventor:

Jeffrey Schulz, Milpitas, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); H03K 19/00 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0008 (2013.01); H03K 19/003 (2013.01); H03K 19/17728 (2013.01); H03K 19/17744 (2013.01);
Abstract

Input-output (IO) circuitry for optimizing power management on an integrated circuit is disclosed. The IO circuitry includes monitoring circuitry and a multiplexer circuit that is controlled by the monitoring circuitry. The monitoring circuitry determines whether majority of the bits of an IO signal are transitioning from a first logical state to a second logical state. When a number of bit transitions of the IO signal exceeds a predetermined bit transition threshold, the monitoring circuitry may send a monitoring circuitry output to the multiplexer circuit to selectively couple an output signal to either the IO signal or an inverted IO signal. The IO circuitry further includes an additional multiplexer that receives the monitoring circuitry output and a clock signal. The additional multiplexer selects an additional output signal from the monitoring circuitry output and the clock signal based on a control signal that indicates a power-savings operation.


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