The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

Mar. 04, 2015
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventor:

Mitsuyoshi Endo, Yamato, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/54 (2010.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 33/20 (2010.01); H01L 33/62 (2010.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 33/54 (2013.01); H01L 21/6836 (2013.01); H01L 24/96 (2013.01); H01L 33/0095 (2013.01); H01L 21/561 (2013.01); H01L 33/20 (2013.01); H01L 33/62 (2013.01); H01L 2221/68322 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68336 (2013.01); H01L 2221/68368 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/18 (2013.01); H01L 2924/18162 (2013.01); H01L 2933/005 (2013.01); H01L 2933/0033 (2013.01);
Abstract

According to one embodiment, a manufacturing method of a semiconductor device includes the transferring a first group from a first support to a second support; the deforming the second support to convert each pitch of the semiconductor chips in the first group transferred on the second support into a second pitch different from the first pitch; the forming an insulating layer around each of the semiconductor chips, the insulating layer covering each of the semiconductor chips in the first group arranged in the second pitch; and the dicing the insulating layer. The first group is selected from a plurality of semiconductor chips supported by the first support. The plurality of semiconductor chips is arranged in an initial pitch. The first group is arranged in a first pitch being longer than the initial pitch.


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