The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

Aug. 16, 2016
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Optoelectronics Technology Co., Ltd., Beijing, CN;

Inventors:

Tiansheng Li, Beijing, CN;

Jing Li, Beijing, CN;

Wenyu Zhang, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 27/32 (2006.01); G02F 1/1368 (2006.01); G02F 1/1335 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H01L 27/1259 (2013.01); H01L 27/3262 (2013.01); G02F 1/1368 (2013.01); G02F 1/133514 (2013.01); G02F 1/134309 (2013.01); G02F 2201/123 (2013.01);
Abstract

An array substrate and a method of manufacturing the same, a display panel and a display device are disclosed. The array substrate includes: a base substrate, and a first conductive layer, a first insulation layer, a semiconductor layer, a second conductive layer, a second insulation layer, and a third conductive layer that are sequentially formed on the base substrate. The first conductive layer includes a gate electrode pattern, the semiconductor layer includes an active area pattern, and the second conductive layer includes a source-drain electrode pattern; the second insulation layer is provided with a connection via hole between the third conductive layer and the second conductive layer; and the semiconductor layer further includes a spacing pad pattern in a region where the connection via hole is provided.


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