The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2017
Filed:
Jul. 15, 2016
Applicant:
Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;
Inventors:
Tadatoshi Danno, Tokyo, JP;
Atsushi Nishikizawa, Tokyo, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 23/495 (2006.01); H01L 25/00 (2006.01); H01L 25/07 (2006.01); H01L 23/047 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/73 (2013.01); H01L 21/4853 (2013.01); H01L 23/047 (2013.01); H01L 23/3675 (2013.01); H01L 23/49575 (2013.01); H01L 23/49827 (2013.01); H01L 23/49844 (2013.01); H01L 24/09 (2013.01); H01L 24/33 (2013.01); H01L 24/45 (2013.01); H01L 24/49 (2013.01); H01L 23/3121 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49107 (2013.01); H01L 2224/49171 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15159 (2013.01);
Abstract
An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted.