The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

Mar. 07, 2016
Applicants:

SK Hynix Inc., Icheon, KR;

Seoul National University R&db Foundation, Seoul, KR;

Inventors:

Jong Ho Lee, Seoul, KR;

Ho Jung Kang, Seoul, KR;

Nag Yong Choi, Jeonju, KR;

Byeong Il Han, Icheon, KR;

Kyoung Jin Park, Seoul, KR;

Sung Yong Chung, Seongnam, KR;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/16 (2006.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 29/792 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); G11C 16/3472 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01); H01L 29/792 (2013.01);
Abstract

A data storage device includes a non-volatile memory device, which includes a memory cell array including a plurality of memory cells and a control circuit. Each of the memory cells includes a channel layer, a charge trap layer on the channel layer, and a control electrode on the charge trap layer, the charge trap layer being shared by the memory cells. The charge trap layer includes program regions respectively disposed below the control electrodes of the memory cells, and charge spread blocking regions, each of which is disposed between two adjacent ones of the program regions and between two adjacent ones of the control electrodes. The control circuit controls the memory cell array so that a potential barrier is generated in the charge spread blocking regions by charging the charge spread blocking regions with charges having the same polarity as that of program charges stored in the program regions.


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