The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

Jun. 30, 2016
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Per Torstein Roine, Oslo, NO;

Vinod Menezes, Bangalore, IN;

Mahesh Mehendale, Karnataka, IN;

Vamsi Gullapalli, Karnataka, IN;

Premkumar Seetharaman, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 11/419 (2006.01); G11C 11/4094 (2006.01); G11C 7/10 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 7/1018 (2013.01); G11C 7/1039 (2013.01); G11C 7/12 (2013.01); G11C 11/4094 (2013.01); G11C 11/412 (2013.01);
Abstract

In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines.


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