The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2017
Filed:
Dec. 06, 2011
Applicants:
Hamid Khodabandehlou, Milpitas, CA (US);
Syed Babar Raza, San Jose, CA (US);
Inventors:
Hamid Khodabandehlou, Milpitas, CA (US);
Syed Babar Raza, San Jose, CA (US);
Assignee:
Cypress Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/406 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1072 (2013.01); G11C 7/1039 (2013.01); G11C 7/1045 (2013.01); G11C 7/22 (2013.01); G11C 11/40615 (2013.01);
Abstract
A method of operating a memory interface circuit involves selectively operating the memory interface in either a synchronous mode or an asynchronous mode, the synchronous mode controlled by a first clock signal; in asynchronous mode, controlling an address latch for latching an address of a memory location in a memory array, the address latch controlled by an asynchronous address control signal synchronized to a second clock signal that is faster than a third clock signal used to operate the memory array.