The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2017
Filed:
Jun. 15, 2015
Lawrence T. Clark, Phoenix, AZ (US);
Dan Wheeler Patterson, Scottsdale, AZ (US);
Chandarasekaran Ramamurthy, Tempe, AZ (US);
Srivatsan Chellappa, Tempe, AZ (US);
Lawrence T. Clark, Phoenix, AZ (US);
Dan Wheeler Patterson, Scottsdale, AZ (US);
Chandarasekaran Ramamurthy, Tempe, AZ (US);
Srivatsan Chellappa, Tempe, AZ (US);
Arizona Board of Regents on behalf of Arizona State University, Scottsdale, AZ (US);
Abstract
This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing.