The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2017
Filed:
Jul. 03, 2015
Applicant:
Hyperion Core Inc., Los Gatos, CA (US);
Inventor:
Martin Vorbach, Lingenfeld, DE;
Assignee:
Hyperion Core, Inc., Los Gatos, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0815 (2016.01); G06F 9/52 (2006.01); G06F 12/0811 (2016.01); G06F 12/0813 (2016.01); G06F 12/0842 (2016.01); G06F 12/0893 (2016.01); G06F 12/084 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0815 (2013.01); G06F 9/526 (2013.01); G06F 12/084 (2013.01); G06F 12/0811 (2013.01); G06F 12/0813 (2013.01); G06F 12/0842 (2013.01); G06F 12/0893 (2013.01); G06F 2212/271 (2013.01); G06F 2212/50 (2013.01); G06F 2212/62 (2013.01); Y02B 60/1225 (2013.01);
Abstract
The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.