The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

Dec. 18, 2013
Applicant:

Avago Technologies General Ip (Singapore) Pte. Ltd., Singapore, SG;

Inventors:

Saugata Das Purkayastha, Bangalore, IN;

Luca Bert, Cumming, GA (US);

Horia Simionescu, Foster City, CA (US);

Kishore Kaniyar Sampathkumar, Bangalore, IN;

Mark Ish, Atlanta, GA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/0811 (2016.01); G06F 12/0886 (2016.01); G06F 12/0846 (2016.01); G06F 12/122 (2016.01); G06F 12/0891 (2016.01); G06F 12/0866 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 12/0846 (2013.01); G06F 12/0866 (2013.01); G06F 12/0886 (2013.01); G06F 12/0891 (2013.01); G06F 12/122 (2013.01);
Abstract

An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the cache-lines comprises a plurality of sub-cache lines. Each of the plurality of cache-lines and each of the plurality of sub-cache lines is associated with meta-data indicating one or more of a dirty state and an invalid state. The controller is connected to the memory and configured to (i) recognize sub-cache line boundaries and (ii) process the I/O requests in multiples of a size of said sub-cache lines to minimize cache-fills.


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