The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

Jan. 13, 2016
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Kumiko Nomura, Tokyo, JP;

Shinobu Fujita, Tokyo, JP;

Keiko Abe, Kanagawa, JP;

Kazutaka Ikegami, Kanagawa, JP;

Hiroki Noguchi, Kanagawa, JP;

Susumu Takeda, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0802 (2016.01); G06F 1/26 (2006.01); G06F 1/32 (2006.01); G06F 12/0897 (2016.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0802 (2013.01); G06F 1/26 (2013.01); G06F 1/32 (2013.01); G06F 12/0897 (2013.01); G11C 11/1697 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/222 (2013.01); G06F 2212/60 (2013.01); G06F 2212/601 (2013.01); Y02B 60/1225 (2013.01);
Abstract

A memory control circuit has a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to n-th level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first nonvolatile memory, and a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry.


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