The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

Jun. 07, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Eric M. Schwarz, Gardiner, NY (US);

Ronald M. Smith, Sr., Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/302 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/3802 (2013.01); G06F 9/3836 (2013.01);
Abstract

A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.


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