The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Apr. 27, 2016
Applicant:

Xpliant, Inc., San Jose, CA (US);

Inventors:

Weihuang Wang, Los Gatos, CA (US);

Mohan Balan, Santa Clara, CA (US);

Nimalan Siva, San Ramon, CA (US);

Zubin Shah, Santa Clara, CA (US);

Assignee:

Cavium, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01); H04L 12/745 (2013.01); H04L 12/753 (2013.01); H04L 12/749 (2013.01);
U.S. Cl.
CPC ...
H04L 45/748 (2013.01); H04L 45/48 (2013.01); H04L 45/741 (2013.01);
Abstract

A network switch includes a memory configurable to store alternate table representations of an individual trie in a hierarchy of tries. A prefix table processor accesses in parallel, using an input network address, the alternate table representations of the individual trie and searches for a longest prefix match in each alternate table representation to obtain local prefix matches. The longest prefix match from the local prefix matches is selected. The longest prefix match has an associated next hop index base address and offset value. A next hop index processor accesses a next hop index table in the memory utilizing the next hop index base address and offset value to obtain a next hop table pointer. A next hop processor accesses a next hop table in the memory using the next hop table pointer to obtain a destination network address.


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