The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Aug. 22, 2014
Applicant:

Taiyo Yuden Co., Ltd., Tokyo, JP;

Inventors:

Masayuki Satou, Tokyo, JP;

Isao Shimizu, Saitama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); H03K 19/0948 (2006.01); G11C 7/06 (2006.01); G11C 8/10 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1776 (2013.01); G11C 7/06 (2013.01); G11C 8/10 (2013.01); H03K 19/0948 (2013.01); H03K 19/17728 (2013.01); H03K 19/17736 (2013.01);
Abstract

There is provided a logic device including memory cell units. Each of the memory cell units includes a pair of bit lines arranged corresponding to a column of memory cells, a word line, and an inverter unit connected to the pair of bit lines. The inverter unit includes a first CMOS and a second CMOS. The first CMOS is configured to receive an input signal from one of the pair of bit lines. The first CMOS includes a first MOS transistor and a second MOS transistor. The second CMOS is configured to receive an input signal from the other of the pair of bit lines. The second CMOS includes a third MOS transistor and a fourth MOS transistor. The inverter unit is configured to output a first differential signal and a second differential signal as a data signal.


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