The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Feb. 03, 2016
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Hikaru Tamura, Kanagawa, JP;

Naoaki Tsutsui, Kanagawa, JP;

Atsuo Isobe, Kanagawa, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H03K 19/00 (2006.01); H01L 29/786 (2006.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0008 (2013.01); H01L 27/0688 (2013.01); H01L 27/1207 (2013.01); H01L 29/7869 (2013.01); H01L 27/0207 (2013.01);
Abstract

To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.


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