The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Apr. 30, 2015
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventor:

Santosh Astgimath, Edinburgh, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 99/00 (2009.01); H04R 3/00 (2006.01); H03F 3/50 (2006.01); H03F 1/26 (2006.01); H03F 3/183 (2006.01); H03F 3/187 (2006.01); H03F 1/02 (2006.01); H03G 1/00 (2006.01); H03G 3/00 (2006.01);
U.S. Cl.
CPC ...
H03F 3/505 (2013.01); H03F 1/0205 (2013.01); H03F 1/26 (2013.01); H03F 3/183 (2013.01); H03F 3/187 (2013.01); H03G 1/0088 (2013.01); H04R 3/00 (2013.01); H03F 2200/03 (2013.01); H03F 2200/129 (2013.01); H03F 2200/15 (2013.01); H03F 2200/24 (2013.01); H03F 2200/294 (2013.01); H04R 2201/003 (2013.01);
Abstract

This application relates to amplifier circuitry for amplifying a signal from a MEMS transducer. A super source follower circuit () is provided which includes a feedback path from its output node (N) to a control bias node (BC) in order to provide a preamplifier signal gain that may be greater than unity. A first transistor (M) is configured to have its gate node connected to an input node (N) for receiving the input signal (V) and its drain node connected to an input node (X) of an output stage (A). The source node of the first transistor is connected to the output node (N). A current source (I) is configured to deliver a current to the drain node of the first transistor (M), wherein the current source (I) is controlled by a bias control voltage (V) at the bias control node (BC). A feedback impedance network (Z) comprising a first port connected to the output node (N) and a second port connected to the bias control node (BC) is provided.


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