The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2017
Filed:
Jun. 05, 2015
Applicant:
Lumentum Operations Llc, Milpitas, CA (US);
Inventors:
Kong Weng Lee, San Jose, CA (US);
Vincent V. Wong, Los Altos, CA (US);
Jay A. Skidmore, San Jose, CA (US);
Jihua Du, Santa Clara, CA (US);
Assignee:
Lumentum Operations LLC, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01S 3/04 (2006.01); H01S 5/022 (2006.01); H01S 5/024 (2006.01);
U.S. Cl.
CPC ...
H01S 5/02272 (2013.01); H01S 5/022 (2013.01); H01S 5/02256 (2013.01); H01S 5/02268 (2013.01); H01S 5/02476 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48464 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/16151 (2013.01); H01L 2924/16152 (2013.01); H01S 5/02236 (2013.01); H01S 5/02276 (2013.01); H01S 5/02296 (2013.01); H01S 5/02469 (2013.01);
Abstract
A chip-scale package for an edge-emitting semiconductor device and a semiconductor device assembly including such a chip-scale package are provided. The chip-scale package includes an edge-emitting semiconductor device chip, a top submount disposed on a top surface of the chip, and a bottom submount disposed on a bottom surface of the chip. The top-submount area and the bottom-submount area are each greater than the chip area and less than or equal to about 1.2 times the chip area.