The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2017
Filed:
Nov. 30, 2014
Applicant:
Tower Semiconductor Ltd., Migdal Haemek, IL;
Inventors:
Assignee:
Tower Semiconductor Ltd., Migdal Haemek, IL;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7809 (2013.01); H01L 21/823487 (2013.01); H01L 21/823885 (2013.01); H01L 27/088 (2013.01); H01L 27/0922 (2013.01); H01L 29/41741 (2013.01); H01L 29/4916 (2013.01); H01L 21/82385 (2013.01); H01L 21/823857 (2013.01);
Abstract
A vertical DMOS device implements one or more deep silicon via (DSV) plugs, thereby significantly reducing the layout area and on-resistance (RDS) of the device. The DSV plugs extend through a semiconductor substrate to contact a conductively doped buried diffusion region, which forms the drain of the vertical DMOS device. Methods for fabricating the vertical DMOS device are compatible with conventional sub-micron VLSI processes, such that the vertical DMOS device can be readily fabricated on the same integrated circuit as CMOS devices and analog devices, such as lateral double-diffused MOS (LDMOS) devices.