IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9728607 B1

PDFFull Text
Date of Patent:
Aug. 08, 2017

Filed:

Jan. 17, 2014

Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Applicant:

Sumitomo Electric Industries, Ltd., Osaka-shi, JP;

Inventors:

Taku Horii, Osaka, JP;

Masaki Kijima, Itami, JP;

Assignee:

Sumitomo Electric Industries, Ltd., Osaka-shi, JP;

Attorneys:

Venable LLP

Michael A. Sartori

Laura G. Remus

Primary Examiner:

Michael Lebentritt

Assistant Examiner:

Jordan Klein

Int. Cl.
CPC ...
H01L 29/16 (2006.01); H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/04 (2006.01); H01L 21/311 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 21/02164 (2013.01); H01L 21/048 (2013.01); H01L 21/28 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76804 (2013.01); H01L 21/76844 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5329 (2013.01); H01L 23/53266 (2013.01); H01L 29/66068 (2013.01); H01L 29/78 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A silicon carbide substrate having a gate insulating film provided in contact with a first main surface, having a gate electrode provided in contact with the gate insulating film, and having a source region exposed from first main surface is prepared. A first recess having a first inner wall surface is formed in an interlayer insulating film by performing a first isotropic etching with respect to the interlayer insulating film with use of a mask layer. A second recess having a second inner wall surface is formed by performing a first anisotropic etching with respect to the interlayer insulating film and the gate insulating film with use of the mask layer and thereby exposing the source region from gate insulating film. An interconnection is formed which is arranged in contact with the first inner wall surface and the second inner wall surface and electrically connected to a source electrode.

Find Patent Forward Citations

Loading…