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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9728441 B1

PDFFull Text
Date of Patent:
Aug. 08, 2017

Filed:

Sep. 03, 2015

Method for manufacturing semiconductor device

Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventors:

Masaaki Tachioka, Matsumoto, JP;

Tsunehiro Nakajima, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:

Thanh T Nguyen

Int. Cl.
CPC ...
H01L 21/268 (2006.01); H01L 21/683 (2006.01); C09J 183/06 (2006.01); B23K 26/00 (2014.01); C09J 183/08 (2006.01); H01L 21/762 (2006.01); H01L 21/20 (2006.01); B23K 101/40 (2006.01); B23K 103/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6835 (2013.01); B23K 26/0006 (2013.01); B23K 26/0057 (2013.01); C09J 183/06 (2013.01); C09J 183/08 (2013.01); H01L 21/268 (2013.01); B23K 2201/40 (2013.01); B23K 2203/56 (2015.10); H01L 21/2007 (2013.01); H01L 21/76254 (2013.01); H01L 21/76259 (2013.01); H01L 2221/68318 (2013.01); H01L 2221/68381 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes: bonding at least a part of the rear surface of a semiconductor wafer, and a supporting substrate in use of using a silane coupling agent; forming a functional structure on a front surface of the semiconductor wafer; placing a condensation point of laser light transmitted through the semiconductor wafer on a bonding interface between the semiconductor wafer and the supporting substrate, and irradiating the bonding interface with the laser light, thereby forming a fracture layer on at least a part of an outer circumferential section of the bonding interface; separating the bonding interface; and carrying out rear surface processing on the rear surface of the semiconductor wafer.

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