The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Oct. 01, 2015
Applicant:

Marvell World Trade Ltd., St. Michael, BB;

Inventor:

Pantas Sutardja, Los Gatos, CA (US);

Assignee:

Marvell World Trade Ltd., St. Michael, BB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G11C 16/349 (2013.01); G11C 16/3495 (2013.01); G06F 2212/1036 (2013.01); G06F 2212/7208 (2013.01); G06F 2212/7211 (2013.01);
Abstract

A storage drive including a first and second memories and a controller. The second memory has a write cycle lifetime that is less than a write cycle lifetime of the first memory. Each of the first and second memories includes solid-state memory. The controller: determines a write frequency for a first logical address; and based on the write frequency, determines a write frequency ranking for the first logical address. The write frequency ranking is based on a weighted time-decay average of write counts or an average of elapsed times of write cycles. The controller also: determines whether the write frequency ranking is greater than a lowest write frequency ranking of logical addresses of the first memory; and if the write frequency ranking of the first logical address is greater, maps the logical address with the lowest write frequency ranking in the first memory to the second memory.


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