The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Dec. 22, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

In-Hwan Choi, Hwaseong-si, KR;

ByungJune Song, Suwon-si, KR;

Bomi Kim, Goyang-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Sunwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 8/08 (2006.01); G11C 16/08 (2006.01); G11C 29/02 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/06 (2013.01); G06F 3/0655 (2013.01); G06F 3/0688 (2013.01); G11C 8/08 (2013.01); G11C 16/08 (2013.01); G11C 29/021 (2013.01); G11C 29/025 (2013.01); G11C 29/028 (2013.01); G11C 2029/1202 (2013.01);
Abstract

A nonvolatile memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes memory blocks each having a plurality of pages and performs a read operation on the plurality of pages on the basis of read voltages. The memory controller is configured to manage page serial numbers of some of the plurality of pages according to a program elapsed time of each of the plurality of pages. When the memory controller receives a read command and a logical address from an external device, the memory controller is configured to select at least one of the managed page serial numbers, to compare the selected at least one of the page serial numbers with a page serial number of a page corresponding to the received logical address, and to control levels of the read voltages according to a comparison result.


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