The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Oct. 26, 2015
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Byung Duk Yang, Cupertino, CA (US);

Szu-Hsien Lee, Cupertino, CA (US);

Kyung Wook Kim, Cupertino, CA (US);

Shih Chang Chang, Cupertino, CA (US);

Chun-Yao Huang, Cupertino, CA (US);

Hao-Lin Chiu, Campbell, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/041 (2006.01); G06F 3/044 (2006.01); G09G 3/36 (2006.01); G02F 1/1345 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G09F 9/30 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0416 (2013.01); G02F 1/1345 (2013.01); G02F 1/1368 (2013.01); G02F 1/136286 (2013.01); G06F 3/044 (2013.01); G06F 3/0412 (2013.01); G09F 9/30 (2013.01); G09G 3/3648 (2013.01); G09G 3/3666 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/124 (2013.01); G02F 2001/13456 (2013.01); G06F 2203/04103 (2013.01); G06F 2203/04104 (2013.01); G06F 2203/04112 (2013.01);
Abstract

A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.


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