The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Dec. 19, 2013
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, JP;

Inventors:

Hiromi Notani, Kawasaki, JP;

Takayuki Fukuoka, Kawasaki, JP;

Takashi Yamaki, Kawasaki, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Kawasaki-Shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01);
U.S. Cl.
CPC ...
G06F 1/263 (2013.01);
Abstract

In an active mode, a VDD line receives an internal power supply voltage from an external regulator. A VDD_RAM line receives an internal power supply voltage from an internal regulator. A PMOS switch includes a first PMOS transistor having a source and an N-type well connected to the VDD line, and a second PMOS transistor having a source and an N-type well connected to the VDD_RAM line and a drain connected to a drain of the first PMOS transistor. The first PMOS transistor is controlled based on a control command from a system control circuit and a voltage of the VDD_RAM line. The second PMOS transistor is controlled based on the control command and a voltage of the VDD line.


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