The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Sep. 11, 2014
Applicant:

Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, Guangdong, CN;

Inventors:

Bo Sun, Guangdong, CN;

Hongyuan Xu, Guangdong, CN;

Hsiangchih Hsiao, Guangdong, CN;

Changi Su, Guangdong, CN;

Mian Zeng, Guangdong, CN;

Xiaoxiao Wang, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1368 (2006.01); H01L 21/12 (2006.01); G02F 1/136 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); G02F 1/1335 (2006.01); G02F 1/1343 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/285 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); G02F 1/1362 (2006.01); G02F 1/1333 (2006.01);
U.S. Cl.
CPC ...
G02F 1/1368 (2013.01); G02F 1/136 (2013.01); G02F 1/13439 (2013.01); G02F 1/133514 (2013.01); G02F 1/134309 (2013.01); G02F 1/136227 (2013.01); H01L 21/0273 (2013.01); H01L 21/02422 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/2855 (2013.01); H01L 21/84 (2013.01); H01L 27/12 (2013.01); H01L 27/1218 (2013.01); H01L 27/1222 (2013.01); H01L 27/1288 (2013.01); H01L 29/66765 (2013.01); H01L 29/78669 (2013.01); G02F 2001/133302 (2013.01); G02F 2001/133519 (2013.01); G02F 2001/136222 (2013.01);
Abstract

The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (), a first metal electrode () on the substrate (), a gate isolation layer () positioned on the substrate () and completely covering the first metal electrode (), an island shaped semiconductor layer () on the gate isolation layer (), a second metal electrode () on the gate isolation layer () and the island shaped semiconductor layer (), a protecting layer () on the second metal electrode (), a color resist layer () on the protecting layer (), a protecting layer () on the color resist layer () and a first pixel electrode layer () on the protecting layer (); a via () is formed on the protecting layer (), the color resist layer () and the protecting layer (), and an organic material layer () fills the inside of the via ().


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