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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9723724 B1

PDFFull Text
Date of Patent:
Aug. 01, 2017

Filed:

Jul. 09, 2014

Wiring substrate, method of manufacturing wiring substrate, component-embedded glass substrate, and method of manufacturing component-embedded glass substrate

Applicant:

Sony Corporation, Tokyo, JP;

Inventors:

Shun Mitarai, Kanagawa, JP;

Shusaku Yanagawa, Kanagawa, JP;

Shinji Rokuhara, Kanagawa, JP;

Shuichi Oka, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:

Sheridan Ross P.C.

Primary Examiner:

Tremesha S Willis

Int. Cl.
CPC ...
H05K 1/16 (2006.01); H05K 3/10 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/30 (2006.01); H01L 27/12 (2006.01); H01L 23/15 (2006.01); H01L 21/48 (2006.01); H01L 23/538 (2006.01); H05K 3/42 (2006.01); H05K 3/46 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H05K 3/10 (2013.01); H01L 21/486 (2013.01); H01L 23/15 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5389 (2013.01); H01L 27/124 (2013.01); H01L 27/1218 (2013.01); H05K 1/115 (2013.01); H05K 1/185 (2013.01); H05K 1/186 (2013.01); H05K 3/30 (2013.01); H05K 3/4697 (2013.01); H01L 27/3276 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/73253 (2013.01); H05K 3/42 (2013.01); H05K 3/4605 (2013.01); Y10T 29/4913 (2015.01); Y10T 29/49155 (2015.01);
Abstract

A method of manufacturing a wiring substrate that has a wiring including a through glass via and is formed of a glass substrate includes forming an alteration layer that penetrates the wiring substrate and is patterned, forming the wiring on a front surface of the wiring substrate in which the alteration layer has been formed, and filling an electrode material in a hole formed by removing the alteration layer, thereby forming the through glass via that connects the wiring on the front surface of the wiring substrate and the wiring on a back surface side thereof.

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