The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Jun. 13, 2016
Applicant:

Hitachi, Ltd., Chiyoda-ku, Tokyo, JP;

Inventors:

Tatsunori Usugi, Tokyo, JP;

Kouzaburou Kurita, Tokyo, JP;

Takemasa Komori, Tokyo, JP;

Junya Nasu, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03K 5/15 (2006.01); H03L 7/08 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H03K 5/15066 (2013.01); H03L 7/0807 (2013.01); H04L 7/033 (2013.01);
Abstract

A skew adjustment circuit includes: flip flop circuits for taking in an input signal in response to first clock signals; a clock phase adjustment circuit for adjusting phases of second clock signals, based on the second clock signals generated based on a reference clock signal and an output signal from the flip flop circuits; a phase interval detection circuit for detecting a phase interval between the first clock signals, based on a reference value; and a phase interval adjustment circuit for performing adjustment such that phase intervals become equal to each other between the second clock signals adjusted by the clock phase adjustment circuit, based on a skew adjustment signal from the phase interval detection circuit. The reference value is obtained by calibration, and the second clock signals adjusted by the phase interval adjustment circuit are provided as the first clock signals to the flip flop circuits.


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