The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2017
Filed:
Apr. 26, 2016
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;
Inventors:
Sunwoo Lee, Incheon, KR;
Sangwoo Lee, Seoul, KR;
Changwon Lee, Gwacheon-si, KR;
Jeonggil Lee, Goyang-si, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11582 (2017.01); H01L 21/28 (2006.01); H01L 27/11578 (2017.01); H01L 29/49 (2006.01); H01L 23/535 (2006.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/28282 (2013.01); H01L 23/535 (2013.01); H01L 27/1157 (2013.01); H01L 27/11578 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01);
Abstract
A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.