The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Dec. 15, 2015
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Mutsumi Okajima, Yokkaichi, JP;

Atsushi Oga, Yokkaichi, JP;

Takeshi Yamaguchi, Yokkaichi, JP;

Hiroyuki Ode, Yokkaichi, JP;

Toshiharu Tanaka, Yokkaichi, JP;

Natsuki Fukuda, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11565 (2013.01); H01L 27/249 (2013.01); H01L 27/2427 (2013.01); H01L 27/2454 (2013.01); H01L 27/2481 (2013.01); H01L 45/06 (2013.01); H01L 45/1253 (2013.01); H01L 45/16 (2013.01);
Abstract

In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.


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