The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Aug. 21, 2014
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Yi-Chiau Huang, Fremont, CA (US);

Yihwan Kim, San Jose, CA (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02587 (2013.01); H01L 21/0237 (2013.01); H01L 21/0245 (2013.01); H01L 21/0254 (2013.01); H01L 21/0262 (2013.01); H01L 21/02373 (2013.01); H01L 21/02378 (2013.01); H01L 21/02389 (2013.01); H01L 21/02439 (2013.01); H01L 21/02502 (2013.01); H01L 21/02521 (2013.01); H01L 21/02524 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/02538 (2013.01); H01L 21/02554 (2013.01); H01L 21/02617 (2013.01); H01L 21/02664 (2013.01); H01L 21/67115 (2013.01);
Abstract

Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top. Whereas conventionally formed buffer layers are often thick, rough and/or defective, the strain relaxed buffer layers formed using the implementations described herein demonstrate improved surface morphology with minimal defects.


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