The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Nov. 29, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Ramesh Raghavan, Bengaluru, IN;

Balaji Jayaraman, Bengaluru, IN;

Rajesh R. Tummuru, Bengaluru, IN;

Thejas Kempanna, Bengaluru, IN;

Janakiraman Viraraghavan, Bengaluru, IN;

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 17/18 (2006.01); G11C 17/16 (2006.01);
U.S. Cl.
CPC ...
G11C 17/18 (2013.01); G11C 17/165 (2013.01); G11C 16/0466 (2013.01);
Abstract

A Multi-Time-Programmable-Memory (MTPM) array architecture, whose structure comprising of having Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) memory elements arranged in a set of twin-pairs coupled by wordlines (WLs), bitlines (BLs) and sourcelines (SLs). More specifically, the use of inactive portions of the MTPM array structure as substitutes for conventional BL write driver areas by utilizing a set of twin-pairs acting in parallel. These substituted twin-pair sets will improve programming efficiency (VGS) and retention (VDS) through a lowering Interconnect (IR) drop and VDS drops at the BL write driver.


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