The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Oct. 06, 2016
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventor:

Kenichi Murooka, San Jose, CA (US);

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/04 (2006.01); G11C 13/00 (2006.01); G11C 7/10 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 7/1006 (2013.01); G11C 13/0002 (2013.01); G11C 13/004 (2013.01); G11C 13/0023 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0033 (2013.01); H01L 27/249 (2013.01); H01L 27/2454 (2013.01); H01L 45/16 (2013.01); G11C 2213/71 (2013.01);
Abstract

A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.


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