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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9721653 B1

PDFFull Text
Expired
Date of Patent:
Aug. 01, 2017

Filed:

Sep. 01, 2016

Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture

Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Tianhong Yan, San Jose, CA (US);

George Samachisa, San Jose, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:

Foley & Lardner LLP

Primary Examiner:

Thong Q Le

Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); B82Y 10/00 (2011.01); G11C 11/56 (2006.01); G11C 13/02 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); G11C 16/10 (2006.01); G11C 11/06 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0007 (2013.01); B82Y 10/00 (2013.01); G11C 11/06035 (2013.01); G11C 11/5614 (2013.01); G11C 11/5678 (2013.01); G11C 11/5685 (2013.01); G11C 13/003 (2013.01); G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0011 (2013.01); G11C 13/0064 (2013.01); G11C 13/0069 (2013.01); G11C 13/025 (2013.01); G11C 16/10 (2013.01); H01L 23/528 (2013.01); H01L 27/249 (2013.01); H01L 27/2409 (2013.01); H01L 27/2436 (2013.01); H01L 27/2481 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/146 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0088 (2013.01); G11C 2213/19 (2013.01); G11C 2213/32 (2013.01); G11C 2213/34 (2013.01); G11C 2213/55 (2013.01); G11C 2213/71 (2013.01); G11C 2213/75 (2013.01); G11C 2213/78 (2013.01); H01L 45/065 (2013.01); H01L 45/08 (2013.01); H01L 45/085 (2013.01); H01L 45/1226 (2013.01); H01L 45/1266 (2013.01); H01L 45/142 (2013.01); H01L 45/143 (2013.01); H01L 45/148 (2013.01); H01L 45/149 (2013.01);
Abstract

A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Find Patent Forward Citations

Yan, Tianhong. (2017). Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture (U.S. Patent No. 9721653). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9721653

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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