The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Sep. 30, 2014
Applicant:

SK Hynix Inc., Icheon-Si, KR;

Inventors:

Min-Hye Lee, Icheon-Si, KR;

Ji-Hyae Bae, Icheon-Si, KR;

Yong-Ho Kim, Icheon-Si, KR;

Assignee:

SK hynix Inc., Icheon-Si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 11/16 (2006.01); H01L 27/22 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1673 (2013.01); G11C 11/1659 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); H01L 27/228 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 2213/74 (2013.01); G11C 2213/78 (2013.01); G11C 2213/79 (2013.01); G11C 2213/82 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01);
Abstract

Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes two variable resistance elements in each storage cell, thereby increasing margin and speed of a read operation. One disclosed electronic device includes a semiconductor memory unit which, in one implementation, in addition to two variable resistance elements, further includes a bit line and a bit line bar formed at a metal level; a first word line formed at a transistor level lower than the metal level, and extended in a direction perpendicular to the bit line or the bit line bar; a first selecting element formed at the transistor level and coupled to the bit line and the first word line; a second selecting element formed at the transistor level and coupled to the bit line bar and the first word line.


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