The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2017
Filed:
Jul. 28, 2015
Oracle International Corporation, Redwood Shores, CA (US);
Mamata Godthi, San Jose, CA (US);
Chandan Shantharaj, San Jose, CA (US);
Claire Shih, Santa Clara, CA (US);
Oracle International Corporation, Redwood Shores, CA (US);
Abstract
A method for designing an integrated circuit. The method may include obtaining a register-transfer level (RTL) file for the integrated circuit. The RTL file may include hardware description language code that describes various modules for the integrated circuit. The method may further include selecting, within the RTL file, various state elements having a predetermined clock skew. The method may further include associating, in response to selecting the state elements, the state elements with a predetermined clock header. The method may further include generating a gate-level netlist using the RTL file. The state elements may be assigned to the predetermined clock header in the gate-level netlist. The method may further include generating, using the gate-level netlist, a clock network for the integrated circuit. The state elements in the clock network may have the predetermined clock skew.